1. Field of the Invention
The present invention relates to methods for operating page buffers in nonvolatile memory devices and more particularly, to methods for operating a page buffer of a NAND flash memory device.
2. Discussion of Related Art
Semiconductor memory devices are known to use electrically programmable and erasable components with refresh functions for restoring data in predetermined periods. Herein, “programming” means an operation to write data in memory cells.
NAND flash memory devices have strings containing a number of memory cells serially connected to enable a high integration of a memory device (i.e., adjacent memory cells share a drain or source). NAND flash memory devices are types of memory devices that are configured to read out information in a sequence, which is different from NOR flash memory devices.
A NAND flash memory device employs page buffers to store a large amount of data into memory cells or to read out information from the memory cells. The page buffers receive a large amount of data through input/output pads and then provide the data to the memory cells, or output the data after storing the data of the memory cells. The page buffer can consist of a single register to temporarily store data, or a dual register to raise a programming speed in programming a large amount of data.
A copy-back function is required when memory cells are defective. Data in defective memory cells is transferred to other normal memory cells by way of the page buffers.
FIG. 1 is a block diagram showing a copy-back programming operation in a conventional NAND flash memory device.
Referring to FIG. 1, a conventional copy-back programming operation includes the steps of: reading out a data bit of a defective memory cell of a memory cell array 10 through a bitline (e.g., BLe) selected by a bitline selection/bias circuit 21 and a sensing node SO and then storing the read data bit into a main latch circuit 23 of a page buffer 20 (step 41); transferring the data bit from the main latch circuit 23 to a cache latch circuit 24 (step 42); returning the data bit from the cache latch circuit 24 to the main latch circuit 23 (step 43); and then reprogramming the data bit of the main latch circuit 23 in another memory cell (a normal memory cell) by way of the selected bitline and the sensing line SO (step 44).
However, such a copy-back programming scheme can result in a high probability of errors while transferring data between the main latch circuit 23 and the cache latch circuit 24.